Wafers on which integrated circuits are formed are commonly measured to determine the skew of the manufacturing process used to form the integrated circuits. The skew can affect the ability of the integrated circuits to operate at speeds, temperatures, and voltages at which the integrated circuits were designed to operate. The skew can be characterized by a process corner. In one naming convention, three corners exist: typical (T), fast (F), and slow (S). Fast and slow corners exhibit carrier mobilities that are higher and lower than normal, respectively. Process skew can result from, for example, source/drain epitaxial growth, dopant implantations for wells, channels, and source/drains, gate sidewall spacer width, gate dielectric (e.g., oxide) processing, and gate work-function tuning metal layer thicknesses. In this convention, two-letter designations are used, where the first letter refers to the n-type transistor corner and the second letter refers to the p-type transistor corner. This characterization can be relevant to the use of the integrated circuit and/or the environment in which the integrated circuit is capable of operating.